The trend in CMOS devices is toward decreased size. However, scaling down in size generally degrades device performance. For example, planar CMOS device performance deteriorates when it is scaled down to the 32/20 nm node. Consequently, fin field effect transistors (finFETs) have been developed. FinFETs may have better electrostatic or short channel effect (SCE) control than planar CMOS devices at the 22/14 nm node. FinFET devices are thus replacing planar CMOS devices at smaller scales.
Various technologies that have improved the performance of planar CMOS devices are desired to be extended to finFET devices to improve finFET device operation. One such technology is embedded source/drain (eSD) technology. The eSD technology provides a desired channel strain when suitable epitaxial materials, such as doped eSiGe for pFETs or doped eSi:C for nFETs, are grown adjacent to the channel. Such changes improve performance in planar CMOS devices. However, the change in architecture from a planar to a fin structure may diminish the benefits achieved from technologies such as eSD. Issues from scaling down, such as source-drain merging with neighboring devices and the volume reduction of the source and drain, may also negatively impact performance.
An alternative approach, raised source-drain (rSD), grows the source/drain regions around the un-recessed silicon fin adjacent to the spacer in a cladding-like manner. Consequently, this approach is also termed cladding source-drain (cSD) herein. This growth is followed by a high temperature anneal(s) to drive the dopants into the undoped fin. The anneal temperatures for such high-temperature anneals are in excess of one thousand degrees Celsius. Although rSD may have advantages, there are still issues to be resolved. For example, simultaneously achieving the high doping concentration of the S/D and the high junction steepness has proven challenging because of the high temperature anneal and the lack of a snow plow effect. In order to drive the dopants, native oxides on the interface are removed to preclude the use of even higher temperature anneals. The junction resistance may also be undesirably increased because of dilution of the dopants. The junction steepness may also be reduced. The high thermal stress due to the anneal may also negatively impact wafer integrity and overall CMOS manufacturability.
Other approaches to improving performance exhibit similar issues in obtaining the desired structures for finFET technology. For example, silicidation approaches deposit a highly doped Si layer on the exposed, undoped fin. A metal layer such as Ti is deposited on the highly doped Si layer. A thermal anneal step is performed to silicide the deposited silicon layer to drive the dopants into the undoped fin. However, the solubilities of dopants in the silicides are relatively high. As a result, the snow plow effect is inefficient. Further, the silicidation continues to consume the semiconductor materials beneath (Si, Ge, etc.) during the subsequent dopant activation anneal. This may complicate the overall source-drain integration.
Thus, various issues exist in attempts to improve the performance of semiconductor devices. However, because of the desire to increase scaling to smaller nodes and improve performance, research in finFET devices ongoing.